1. Field of the Invention
Example embodiments of the present invention relate to a transistor and a method of forming the same, and more particularly, to an electrical node of a transistor and a method of forming the same.
2. Description of the Related Art
A transistor may be formed on a semiconductor substrate having a gate pattern and at least three electrical nodes in a semiconductor device. The electrical nodes may be arranged on the semiconductor substrate using at least a conductive layer. The gate pattern may control the charge flow in the semiconductor substrate. The semiconductor substrate may make contact with the electrical nodes through active regions which may contain impurity regions. The electrical nodes may be arranged on the semiconductor substrate so that they are not located at the sides of the active regions. To reduce current leakage during transistor operation, the electrical nodes may be arranged on the active regions to reduce damage generated during manufacture of the semiconductor device. However, because the semiconductor device may be miniaturized to a submicron unit or less (depending on a desired design rule), the transistor may be formed so that the electrical nodes may be located at the sides of the active regions. Additionally, the electrical nodes may be adjacent to gate patterns. This configuration may increase the current leakage generated during transistor operation.
According to a conventional method of solving the current leakage problem, a dielectric layer is formed on a semiconductor substrate. A contact opening for exposing the semiconductor substrate may be formed in the dielectric layer. A silicon nitride spacer may be formed on the sidewall of the contact opening. A cobalt layer may be formed on the bottom of the contact opening. An ionized metal plasma titanium layer may be formed on the cobalt layer and a titanium nitride layer may be formed thereon using chemical vapor deposition.
Subsequently, the semiconductor substrate having the titanium nitride layer and cobalt layer may undergo a first rapid thermal process to cause reaction between the semiconductor substrate and the cobalt layer to form a cobalt silicide layer. The titanium nitride layer and a non-reactive part of the cobalt layer, and the ionized metal plasma titanium layer may be removed using a wet etching method. The semiconductor substrate having the cobalt silicide layer may be subjected to a second rapid thermal process and a conductive layer may be used to fill the contact opening. While this method may reduce charge loss due to mobile ions of the sidewall of the contact opening (to a submicron unit or less), this method may not reduce the current leakage due to the charges flowing in the semiconductor substrate. This is because the side of the active region is exposed via the contact opening in the photolithographic and etching processes in the so-formed apparatus.